VeriFire

Pre-silicon Design Verification is a complex and growing challenge for a variety of reasons

1. Design complexity of Modern SoCs continues to increase

2. Setting up compute infrastructure and EDA licensing is expensive and takes months

3. Simulation speeds are very slow compared to actual silicon

   1. CPUs with clock frequency of 2.5 Ghz can be simulated at merely 100 Hz

   2. This makes it difficult to simulate all cases the actual silicon will see once deployed

   3. This results in long verification schedules and bug escapes to silicon

4. Debugging of fails takes an unexpectedly large proportion of time

   1. Industry surveys show DV Engineers spend 47% of their time on debug*

How does VeriFire solve all this?

1. Cloud based deployment on AWS EC2 F1 instances saves time and money on infrastructure

2. Accelerated simulation due to native deployment on EC2 F1 FPGAs

   1. Achieve speeds of up to 125 Mhz

3. Paradigm shifting debug methodology

   1. Standardizes and streamlines debug

   2. Accelerates root causes analysis

4. Ability to generate simulation logs from FPGA runs

5. Ability to recreate FPGA fails in simulation for full visibility

*https://blogs.sw.siemens.com/verificationhorizons/2022/12/12/part-8-the-2022-wilson-research-group-functional-verification-study/